Structure of thin film transistor and manufacturing method thereof

ABSTRACT

A method of manufacturing a thin film transistor for solving the drawbacks of the prior art is disclosed. The method includes steps of providing an insulating substrate, sequentially forming a source/drain layer, a primary gate insulating layer, and a first conducting layer on the insulating substrate, etching the first conducting layer to form a primary gate; sequentially forming a secondary gate insulating layer and a second conducting layer on the primary gate; and etching the second conducting layer to form a first secondary gate and a second secondary gate.

FIELD OF THE INVENTION

[0001] The present invention is related to a structure of a thin filmtransistor and a manufacturing method thereof, and more particularly toa structure of a thin film transistor applied to TFT-LCD and amanufacturing method thereof.

BACKGROUND OF THE INVENTION

[0002] Thin film transistor liquid crystal Display (TFT-LCD) has becomeone of the most popular and modem information goods. As result of beinglight, small and portable, having a lower operating voltage, being freeof harmful radiation and suited to production on large scale, TFT-LCDsubstitutes for cathode ray tube display as a caressed computer displaydevice.

[0003] In accordance with the structure of TFT-LCD, Drain of TFT has ahigher electric field while TFT is operating, and there should be anoff-state leakage current resulted while the device is shut down,thereby the application of TFT-LCD being limited.

[0004] Presently, someone provides a lightly doped drain structure and afield induced drain structure for preventing TFT-LCD from the off-stateleakage current. FIG. 1 illustrates a lightly doped drain structure ofthe prior art for solving the problem of the off-state leakage current.The structure includes an insulating substrate 11, a source/drain layer12, a gate insulating layer 13 and a gate layer 14, wherein thesource/drain layer 12 further includes a drain 121, a lightly dopeddrain 1211, a channel 122, a source 123 and a lightly doped source 1231.The electric field of the drain 121 is reduced by means of addinglightly doped regions (i.e. the lightly doped drain 1211 and the lightlydoped source 1231) corresponding to the original source 123 and theoriginal drain 121 respectively near the channel 122, so as to preventfrom the leakage current. However the TFT-LCD with the lightly dopedregions is complex and hard to manufacture. Furthermore the resistancewill increases because of the lightly doped degree. As result of theseries resistance of the drain 121 and the source 123 increasing, theoperating speed of the device reduces and the power dissipationincreases.

[0005] Moreover, another improving structure of field-induction drainhas been disclosed. However it has to add an extra photolithographicprocess for manufacturing the improving structure. The morephotolithographic processes are introduced, the more mis-alignment andinfected defects are resulted. Therefore, the cost and the manufacturingtime of the improving structure must increase and the yield reduces.

[0006] Hence, the present invention is attempted to improve the priorart and provides a structure of a thin film transistor applied to aTFT-LCD and a manufacturing method thereof for preventing TFT-LCD fromthe leakage current.

SUMMARY OF THE INVENTION

[0007] It is one object of the present invention to provide a structureof a thin film transistor applied to TFT-LCD and a manufacturing methodthereof.

[0008] It is another object of the present invention to provide astructure of a thin film transistor and a manufacturing method thereoffor preventing TFT-LCD from the leakage current.

[0009] According to the present invention, the method for manufacturinga thin film transistor, includes steps of providing an insulatingsubstrate, sequentially forming a source/drain layer, a primary gateinsulating layer, and a first conducting layer on the insulatingsubstrate, etching the first conducting layer to form a primary gate,sequentially forming a secondary gate insulating layer and a secondconducting layer on the primary gate, and etching the second conductinglayer to form a first secondary gate and a second secondary gate.

[0010] Certainly, the insulating substrate can be a glass.

[0011] Certainly, the source/drain layer can be a high-dopingsemiconductor layer.

[0012] Certainly, the high-doping semiconductor layer can be high-dopingpolycrystalline silicon.

[0013] Preferably, the source/drain layer includes a drain, a channeland a source.

[0014] Preferably, the channel has a length equal to a sum of a lengthof the primary gate, a width of the secondary insulating layer, a lengthof the first secondary gate and a length of the second secondary gate.

[0015] Certainly, the primary gate insulating layer can be one selectedfrom a silicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), a siliconoxide nitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminumoxide (AlO_(x)) and a mixture thereof.

[0016] Certainly, the first conducting layer can be one selected fromchromium (Cr), molybdenum (Mo), tantalum (Ta), tantalum molybdenum(TaMo), tungsten molybdenum (WMo), aluminum (Al), aluminum silicon(AlSi), copper (Cu) and a mixture thereof.

[0017] Certainly, the step (c) can be executed by means of a reactiveion etching.

[0018] Certainly, the secondary gate insulating layer can be oneselected from a silicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), asilicon oxide nitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), analuminum oxide (AlO_(x)) and a mixture thereof.

[0019] Certainly, the second conducting layer can be one selected fromchromium (Cr), molybdenum (Mo), tantalum (Ta), tantalum molybdenum(TaMo), tungsten molybdenum (WMo), aluminum (Al), aluminum silicon(AlSi), copper (Cu) and a mixture thereof.

[0020] Certainly, the step (e) can be executed by means of a reactiveion etching.

[0021] According to the present invention, the structure of a thin filmtransistor includes an insulating substrate, a source/drain layerdisposed on the insulating substrate, a primary insulating layerdisposed on the source/drain layer, a primary gate disposed on theprimary insulating layer, a secondary insulating layer disposed on theprimary insulating layer, and a secondary gate disposed on the secondaryinsulating layer and insulated from the primary gate via the secondaryinsulating layer.

[0022] Preferably, the secondary insulating layer further includes afirst secondary insulating layer and a second secondary insulatinglayer.

[0023] Preferably, the secondary gate further includes a first secondarygate and a second secondary gate disposed on the first secondaryinsulating layer and the second secondary insulating layer respectively.

[0024] Certainly, the insulating substrate can be a glass.

[0025] Certainly, the source/drain layer can be a high-dopingsemiconductor layer.

[0026] Certainly, the high-doping semiconductor layer can be high-dopingpolycrystalline silicon.

[0027] Preferably, the source/drain layer includes a drain, a channeland a source.

[0028] Preferably, the channel has a length equal to a sum of a lengthof the primary gate, a width of the secondary insulating layer, and alength of the secondary gate.

[0029] Certainly, the primary gate insulating layer can be one selectedfrom a silicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), a siliconoxide nitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminumoxide (AlO_(x)) and a mixture thereof.

[0030] Certainly, the first conducting layer can be one selected fromchromium (Cr), molybdenum (Mo), tantalum (Ta), tantalum molybdenum(TaMo), tungsten molybdenum (WMo), aluminum (Al), aluminum silicon(AlSi), copper (Cu) and a mixture thereof.

[0031] Certainly, the primary gate can be formed by means of a reactiveion etching.

[0032] Certainly, the secondary gate insulating layer can be oneselected from a silicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), asilicon oxide nitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), analuminum oxide (AlO_(x)) and a mixture thereof.

[0033] Certainly, the second conducting layer can be one selected fromchromium (Cr), molybdenum (Mo), tantalum (Ta), tantalum molybdenum(TaMo), tungsten molybdenum (WMo), aluminum (Al), aluminum silicon(AlSi), copper (Cu) and a mixture thereof.

[0034] Certainly, the secondary gate can be formed by means of areactive ion etching.

[0035] According to the present invention, the structure of a thin filmtransistor includes an insulating substrate, a source/drain layerdisposed on the insulating substrate, a primary insulating layerdisposed on the source/drain layer, a primary gate disposed on theprimary insulating layer, at least a secondary insulating layer disposedon the primary insulating layer, and at least a secondary gate disposedon the at least a secondary insulating layer and insulated from theprimary gate via the at least a secondary insulating layer.

[0036] Certainly, the insulating substrate can be a glass.

[0037] Certainly, the source/drain layer can be a high-dopingsemiconductor layer.

[0038] Certainly, the high-doping semiconductor layer can be high-dopingpolycrystalline silicon.

[0039] Preferably, the source/drain layer includes a drain, a channeland a source.

[0040] Preferably, the channel has a length equal to a sum of a lengthof the primary gate, a width of the at least secondary insulating layer,and a length of the at least a secondary gate.

[0041] Certainly, the primary gate insulating layer can be one selectedfrom a silicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), a siliconoxide nitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminumoxide (AlO_(x)) and a mixture thereof.

[0042] Certainly, the at least a secondary gate insulating layer can beone selected from a silicon nitride (SiN_(x)), a silicon oxide(SiN_(x)), a silicon oxide nitride (SiO_(x)N_(y)), a tantalum oxide(TaO_(x)), an aluminum oxide (AlO_(x)) and a mixture thereof.

[0043] Now the foregoing and other features and advantages of thepresent invention will be more clearly understood through the followingdescriptions with reference to the drawings, wherein:

BRIEF DESCRIPTION OF THE DRAWINGS

[0044]FIG. 1 illustrates a lightly doped drain structure of the priorart for solving the problem of the off-state leakage current;

[0045] FIGS. 2(a)-2(e) illustrate the steps of manufacturing the thinfilm transistor according to the preferred embodiment of the presentinvention;

[0046]FIG. 3 illustrates electricity properties of the present inventioncompared with those of the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0047] FIGS. 2(a)-2(d) illustrate the steps of manufacturing the thinfilm transistor according to the preferred embodiment of the presentinvention. The method for manufacturing a thin film transistor includesseveral steps. First, an insulating substrate 21 is provided and asource/drain layer 22, a primary gate insulating layer 23, and a firstconducting layer 241 are sequentially formed on the insulating substrate21, shown in FIG. 2(a). Secondly, the first conducting layer 241 isetched to form a primary gate 24, shown in FIG. 2(b). Thirdly, asecondary gate insulating layer 25 and a second conducting layer 26 aresequentially formed on the primary gate 24, shown in FIG. 2(c). Finally,the second conducting layer 26 and the secondary gate insulating layer25 are etched to respectively form a first secondary gate 271 and asecond secondary gate 272, and a first secondary gate insulating layer251 and a second secondary gate insulating layer 252, shown in FIG.2(d). As to FIG. 2(e), it illustrates the bias status of the thin filmtransistor including a source bias voltage (VS) 28, a gate/source biasvoltage (VGS) 29 and a drain/source bias voltage (VDS) 210.

[0048] According to the above embodiment of the present invention, theinsulating substrate 21 is a glass substrate, the source/drain layer 22is a high-doping semiconductor layer, and the high-doping semiconductorlayer is high-doping polycrystalline silicon. Furthermore, thesource/drain layer 22 includes a drain 221, a channel 222 and a source223. Meanwhile, the channel 222 has a length equal to a sum of a lengthof the primary gate 24, a width of the first secondary insulating layer251 and the second secondary insulting layer 252, a length of the firstsecondary gate 271 and the second secondary gate 272.

[0049] As to the primary gate insulating layer 23 and the secondary gateinsulating layer 25, they can be one selected from a silicon nitride(SiN_(x)), a silicon oxide (SiN_(x)), a silicon oxide nitride(SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminum oxide (AlO_(x))and a mixture thereof. However the first conducting layer 241 and thesecond conducting layer 26 are one selected from chromium (Cr),molybdenum (Mo), tantalum (Ta), tantalum molybdenum (TaMo), tungstenmolybdenum (WMo), aluminum (Al), aluminum silicon (AMSi), copper (Cu)and a mixture thereof. Meanwhile, the first conducting layer 241, thesecond conducting layer 26 and the secondary gate insulating layer 25are etched by means of a reactive ion etching.

[0050] Referring to FIG. 3, it illustrates electricity properties of thepresent invention compared with those of the prior art. As result ofoperating the thin film transistor according to the bias status of FIG.2(e), the thin film transistor of the present invention causes a lowerleakage current. In FIG. 3, when the thin film transistor of the presentinvention and the thin film transistor of the prior art are operated inthe same condition (VDS=10V), the leakage current caused by the presentinvention is lower than that caused by the prior art. While VDS=15V, theleakage current (1×10⁻⁹A) of the present invention is 100 times as that(1×10⁻⁷A) of the prior art.

[0051] Accordingly, the present invention reduces the electric field ofthe drain region by means of providing a thicker gate insulating layer,so as to improve the problem of the high off-state leakage current of athin film transistor. Comparing with the prior art, the presentinvention introduces four photolithographic processes equal to thetraditional one, but doesn't have to add an extra photolithographicprocess. Therefore, the present invention can solve the drawbacks of theprior art and be practicability.

[0052] Although the present invention has been described and illustratedin detail, it is to be clearly understood that the same is by the way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A method for manufacturing a thin filmtransistor, comprising steps of: (a) providing an insulating substrate;(b) sequentially forming a source/drain layer, a primary gate insulatinglayer, and a first conducting layer on said insulating substrate; (c)etching said first conducting layer to form a primary gate; (d)sequentially forming a secondary gate insulating layer and a secondconducting layer on said primary gate; and (e) etching said secondconducting layer to form a first secondary gate and a second secondarygate.
 2. The method according to claim 1, wherein said insulatingsubstrate is a glass.
 3. The method according to claim 1, wherein saidsource/drain layer is a high-doping semiconductor layer.
 4. The methodaccording to claim 3, wherein said high-doping semiconductor layer ishigh-doping polycrystalline silicon.
 5. The method according to claim 1,wherein said source/drain layer comprises a drain, a channel and asource.
 6. The method according to claim 5, wherein said channel has alength equal to a sum of a length of said primary gate, a width of saidsecondary insulating layer, a length of said first secondary gate and alength of said second secondary gate.
 7. The method according to claim1, wherein said primary gate insulating layer is one selected from asilicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), a silicon oxidenitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminum oxide(AlO_(x)) and a mixture thereof.
 8. The method according to claim 1,wherein said first conducting layer is one selected from chromium (Cr),molybdenum (Mo), tantalum (Ta), tantalum molybdenum (TaMo), tungstenmolybdenum (WMo), aluminum (Al), aluminum silicon (AlSi), copper (Cu)and a mixture thereof.
 9. The method according to claim 1, wherein saidstep (c) is executed by means of a reactive ion etching.
 10. The methodaccording to claim 1, wherein said secondary gate insulating layer isone selected from a silicon nitride (SiN_(x)), a silicon oxide(SiN_(x)), a silicon oxide nitride (SiO_(x)N_(y)), a tantalum oxide(TaO_(x)), an aluminum oxide (AlO_(x)) and a mixture thereof.
 11. Themethod according to claim 1, wherein said second conducting layer is oneselected from chromium (Cr), molybdenum (Mo), tantalum (Ta), tantalummolybdenum (TaMo), tungsten molybdenum (WMo), aluminum (Al), aluminumsilicon (AlSi), copper (Cu) and a mixture thereof.
 12. The methodaccording to claim 1, wherein said step (e) is executed by means of areactive ion etching.
 13. A structure of a thin film transistorcomprising: an insulating substrate; a source/drain layer disposed onsaid insulating substrate; a primary insulating layer disposed on saidsource/drain layer; a primary gate disposed on said primary insulatinglayer; a secondary insulating layer disposed on said primary insulatinglayer; and a secondary gate disposed on said secondary insulating layerand insulated from said primary gate via said secondary insulatinglayer.
 14. The structure according to claim 13, wherein said secondaryinsulating layer further comprises a first secondary insulating layerand a second secondary insulating layer.
 15. The structure according toclaim 14, wherein said secondary gate further comprises a firstsecondary gate and a second secondary gate disposed on said firstsecondary insulating layer and said second secondary insulating layerrespectively.
 16. The structure according to claim 13, wherein saidinsulating substrate is a glass.
 17. The structure according to claim13, wherein said source/drain layer is a high-doping semiconductorlayer.
 18. The structure according to claim 17, wherein said high-dopingsemiconductor layer is high-doping polycrystalline silicon.
 19. Thestructure according to claim 13, wherein said source/drain layercomprises a drain, a channel and a source.
 20. The structure accordingto claim 19, wherein said channel has a length equal to a sum of alength of said primary gate, a width of said secondary insulating layer,and a length of said secondary gate.
 21. The structure according toclaim 13, wherein said primary gate insulating layer is one selectedfrom a silicon nitride (SiN_(x)), a silicon oxide (SiN_(x)), a siliconoxide nitride (SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminumoxide (AlO_(x)) and a mixture thereof.
 22. The structure according toclaim 13, wherein said first conducting layer is one selected fromchromium (Cr), molybdenum (Mo), tantalum (Ta), tantalum molybdenum(TaMo), tungsten molybdenum (WMo), aluminum (Al), aluminum silicon(AlSi), copper (Cu) and a mixture thereof.
 23. The structure accordingto claim 13, wherein said primary gate is formed by means of a reactiveion etching.
 24. The structure according to claim 13, wherein saidsecondary gate insulating layer is one selected from a silicon nitride(SiN_(x)), a silicon oxide (SiN_(x)), a silicon oxide nitride(SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminum oxide (AlO_(x))and a mixture thereof.
 25. The structure according to claim 13, whereinsaid second conducting layer is one selected from chromium (Cr),molybdenum (Mo), tantalum (Ta), tantalum molybdenum (TaMo), tungstenmolybdenum (WMo), aluminum (Al), aluminum silicon (AlSi), copper (Cu)and a mixture thereof.
 26. The structure according to claim 13, whereinsaid secondary gate is formed by means of a reactive ion etching.
 27. Astructure of a thin film transistor comprising: an insulating substrate;a source/drain layer disposed on said insulating substrate; a primaryinsulating layer disposed on said source/drain layer; a primary gatedisposed on said primary insulating layer; at least a secondaryinsulating layer disposed on said primary insulating layer; and at leasta secondary gate disposed on said at least a secondary insulating layerand insulated from said primary gate via said at least a secondaryinsulating layer.
 28. The structure according to claim 27, wherein saidinsulating substrate is a glass.
 29. The structure according to claim27, wherein said source/drain layer is a high-doping semiconductorlayer.
 30. The structure according to claim 29, wherein said high-dopingsemiconductor layer is high-doping polycrystalline silicon.
 31. Thestructure according to claim 27, wherein said source/drain layercomprises a drain, a channel and a source.
 32. The structure accordingto claim 31, wherein said channel has a length equal to a sum of alength of said primary gate, a width of said at least secondaryinsulating layer, and a length of said at least a secondary gate. 33.The structure according to claim 27, wherein said primary gateinsulating layer is one selected from a silicon nitride (SiN_(x)), asilicon oxide (SiN_(x)), a silicon oxide nitride (SiO_(x)N_(y)), atantalum oxide (TaO_(x)), an aluminum oxide (AlO_(x)) and a mixturethereof.
 34. The structure according to claim 29, wherein said at leasta secondary gate insulating layer is one selected from a silicon nitride(SiN_(x)), a silicon oxide (SiN_(x)), a silicon oxide nitride(SiO_(x)N_(y)), a tantalum oxide (TaO_(x)), an aluminum oxide (AlO_(x))and a mixture thereof.